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? 2014-2015 microchip technology inc. ds00001783b-page 1 product features ? usb-if hi-speed certified to the universal serial bus specification rev 2.0 ? interface compliant with the ulpi specification revision 1.1 in 8-bit mode ? industry standard utmi+ low pin interface (ulpi) converts 54 utmi+ signals into a standard 12 pin link controller interface ? 54.7ma unconfigured current (typical) - ideal for bus powered applications ? 83ua suspend current (typical) - ideal for battery powered applications ? latch-up performance exceeds 150 ma per eia/ jesd 78, class ii ? esd protection levels of 8kv hbm without exter- nal protection devices ? integrated protection to withstand iec61000-4-2 esd tests ( 8kv contact and 15kv air) per 3rd party test facility ? supports fs pre-amble for fs hubs with a ls device attached (utmi+ level 3) ? supports hs sof and ls keep-alive pulse ? includes full support for the optional on-the-go (otg) protocol detailed in the on-the-go sup- plement revision 1.0a specification ? supports the otg host negotiation protocol (hnp) and session request protocol (srp) ? allows host to turn vbus off to conserve battery power in otg applications ? supports otg monitoring of vbus levels with internal comparators. includes support for an external vbus or fault monitor. ? low latency hi-speed receiver (43 hi-speed clocks max) allows use of legacy utmi links with a ulpi wrapper ? integrated pull-up resistor on stp for interface protection allows a reliable link/phy start-up with slow links (software configured for low power) ? internal 1.8 volt regulators allow operation from a single 3.3 volt supply ? internal short circuit protection of id, dp and dm lines to vbus or ground ? integrated 24mhz crystal oscillator supports either crystal operation or 24mhz external clock input ? internal pll for 480mhz hi-speed usb operation ? industrial operating temperature -40 c to +85 c ? 32 pin, qfn rohs compliant package (5 x 5 x 0.90 mm height) applications the USB3300 is the ideal companion to any asic, soc or fpga solution designed with a ulpi hi-speed usb host, peripheral or otg core. the USB3300 is well suited for: ? cell phones ?pdas ? mp3 players ? scanners ? external hard drives ? digital still and video cameras ? portable media players ? printers USB3300 hi-speed usb host, device or otg phy with ulpi low pin interface
USB3300 ds00001783b-page 2 ? 2014-2015 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2014-2015 microchip technology inc. ds00001783b-page 3 USB3300 table of contents 1.0 introduction .............................................................................................................. ....................................................................... 4 2.0 functional overview ....................................................................................................... ................................................................ 6 3.0 pin layout ................................................................................................................ ....................................................................... 7 4.0 operational description ................................................................................................... ............................................................. 11 5.0 electrical characteristics ................................................................................................ ............................................................... 12 6.0 architecture overview ..................................................................................................... .............................................................. 16 7.0 application notes ......................................................................................................... ................................................................. 39 8.0 package outline ........................................................................................................... ................................................................. 45 appendix a: data sheet revision history ....................................................................................... .................................................... 48 the microchip web site ........................................................................................................ .............................................................. 50 customer change notification service .......................................................................................... ..................................................... 50 customer support .............................................................................................................. ................................................................. 50 product identification system ................................................................................................. ............................................................ 51
USB3300 ds00001783b-page 4 ? 2014-2015 microchip technology inc. 1.0 introduction 1.1 general description the USB3300 is an industrial temperature hi-speed usb physical layer transceiver (phy). the USB3300 uses a low pin count interface (ulpi) to connect to a ulpi compliant link layer. the ulpi interface reduces the utmi+ interface from 54 pins to 12 pins using a method of in-band si gnaling and status byte transfers between the link and phy. this phy was designed from the start with the ulpi interface. no utmi to ulpi wrappers are used in this design which provides a seamless ulpi to link interface. the result is a phy with a low latency transmit and receive time. microchip?s low latency high speed and full speed receiver provide the option of re-using existing utmi links with a simple wrapper to convert utmi to ulpi. the ulpi interface allows the USB3300 phy to operate as a device, host, or an on-the-go (otg) device. designs using the USB3300 phy as a device, can add host and otg capability at a later date with no additional pins. the ulpi interface, combined with microchip?s proprietary technology, makes the USB3300 the ideal method of adding hi-speed usb to new designs. the USB3300 features an in dustry leading small footprin t package (5mm by 5mm) with sub 1mm height. in addition the USB3300 integrates all dp and dm termination resistances and requires a minimal number of external components. the ulpi interface consists of 12 interface pins; 8 bi-directi onal data pins, 3 control pins, and a 60 mhz clock. by using the 12 pin ulpi interface the USB3300 is able to provide su pport for the full range of utmi+ level 3 through level 0, as shown in figure 1-2 . this allows USB3300 to work as a hs and fs peripheral and as a hs, fs, and ls host. the USB3300 can also, as an option, fully support the on-t he-go (otg) protocol defined in the on-the-go supplement to the usb 2.0 specification. on-the-go allows the USB3300 to function like a host, or peripheral configured dynamically by software. for example, a cell phone may connect to a computer as a peripheral to exchange address information or connect to a printer as a host to pr int pictures. finally the otg enabled device can connect to another otg enabled device to exchange information. all this is supported using a single low profile mini-ab usb connector. designs not needing otg can ignore the otg feature set. in addition to the advantages of the leading edge ulpi interface, the use of microchip?s advanced analog technology enables the USB3300 to consume a minimum amount of power which results in maximized battery life for portable appli- cations. figure 1-1: basic ulpi usb device block diagram USB3300 hi-speed analog w/ otg ulpi digital logic usb connector (standard or mini) ulpi link dm v bus dp id stp clk dir nxt data[7:0] 32 pin qfn
? 2014-2015 microchip technology inc. ds00001783b-page 5 USB3300 1.2 reference documents ? universal serial bus specificatio n, revision 2.0, april 27, 2000 ? on-the-go supplement to the usb 2.0 s pecification, revision 1.0a, june 24, 2003 ? usb 2.0 transceiver macrocell interface (utmi) specification, version 1.02, may 27, 2000 ? utmi+ specification, revi sion 1.0, february 2, 2004 ? utmi+ low pin interface (ulpi) specification, revision 1.1 figure 1-2: ulpi interface features as related to utmi+ utmi+ level 0 hi-speed peripherals only added features USB3300 ulpi hi-speed peripheral, ho st controllers, on-the- go devices with 12 pin interface (hs, fs, ls, preamble packet) utmi+ level 3 hi-speed peripheral, host controllers, on- the-go devices (hs, fs, ls, preamble packet) utmi+ level 2 hi-speed peripheral, host controllers, on- the-go devices (hs, fs, and ls but no preamble packet) utmi+ level 1 hi-speed peripheral, host controllers, and on-the-go devices (hs and fs only) usb3500 usb3450 usb3280 usb3250
USB3300 ds00001783b-page 6 ? 2014-2015 microchip technology inc. 2.0 functional overview the USB3300 is a highly integrated usb phy. it contains a complete hi-speed usb 2.0 phy with the ulpi industry standard interface to support fast time to market for a usb product. the USB3300 is composed of the functional blocks shown in figure 2-1 below. details of these indivi dual blocks are described in architecture overview on page 16 . figure 2-1: USB3300 block diagram ulpi digital otg module data[7:0] 24 mhz xtal internal regulator & por 5v power supply bias gen. clkout nxt dir stp vdd3.3 xtal & pll xi cpen vbus id vdd3.3 dp dm USB3300 vdd1.8 vdda1.8 m xo rbias extvbus fault mini-ab usb connector hs xcvr fs/ls xcvr resistors rpu_dp rpd_dm rpd_dp rpu_dm en
? 2014-2015 microchip technology inc. ds00001783b-page 7 USB3300 3.0 pin layout the USB3300 is offered in a 32 pin qfn package (5 x 5 x 0.9mm). the pin definitions and locations are documented below. 3.1 USB3300 pin diagram the exposed flag of the qfn package must be connected to ground with a via array to the ground plane. this is the main ground connection for the USB3300. 3.2 pin function figure 3-1: USB3300 pin diagram - top view table 3-1: USB3300 pin definitions 32-pin qfn package pin name direction, type active level description 1 gnd ground n/a ground 2 gnd ground n/a ground 3 cpen output, cmos high external 5 volt supply enable. this pin is used to enable the external vbus power supply. the cpen pin is low on por. 4 vbus i/o, analog n/a vbus pin of the usb cable. the USB3300 uses this pin for the vbus comparator inputs and for vbus pulsing during session request protocol. 5 id input, analog n/a id pin of the usb cable. for non-otg applications this pin can be floated. for an a-device id = 0. for a b-device id = 1. gnd gnd cpen vbus id vdd3.3 dm dp reset extvbus nxt dir stp clkout vdd3.3 vdd1.8 data0 data7 data5 data6 data2 data3 data4 data1 rbias vdd3.3 xo vdd1.8 vdd3.3 vdda1.8 xi reg_en USB3300 hi-speed usb2 ulpi phy 32 pin qfn 1 2 3 4 5 6 7 8 USB3300 hi-speed usb ulpi phy 32 pin qfn gnd flag 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25
USB3300 ds00001783b-page 8 ? 2014-2015 microchip technology inc. 6 vdd3.3 power n/a 3.3v supply. a 0.1uf bypass capacitor should be connected between this pin and the ground plane on the pcb. 7 dp i/o, analog n/a d+ pin of the usb cable. 8 dm i/o, analog n/a d- pin of the usb cable. 9 reset input, cmos high optional active high transceiver reset. this is the same as a write to the ulpi reset , address 04h, bit 5. this does not reset the ul pi register set. this pin includes an integrated pull-down resistor to ground. if not used, this pin can be floated or connected to ground (recommended). see section 6.1.11, "reset pin" for details. 10 extvbus input, cmos high external vbus detect. connect to fault output of an external usb power switch or an external vbus valid comparator. see section 6.5.4, "external vbus indicator," on page 38 for details. this pin has a pull down resistor to prevent it from floating when the ulpi bit useexternalvbusindicator is set to 0. 11 nxt output, cmos high the phy asserts nxt to throttle the data. when the link is sending data to the phy, nxt indicates when the current byte has been accepted by the phy. the link places the next byte on the data bus in the following clock cycle. 12 dir output, cmos n/a controls the direction of the data bus. when the phy has data to transfer to the link, it drives dir high to take ownership of the bus. when the phy has no data to transfer it drives dir low and monitors the bus for commands from the link. the phy will pull dir high whenever the interface canno t accept data from the link, such as during pll start-up. 13 stp input, cmos high the link asserts stp for one clock cycle to stop the data stream currently on the bus. if the link is sending data to the phy, stp indicates the last byte of data was on the bus in the previous cycle. the stp pin also includes the interface protection detailed in section 6.1.9.3, "interface protection," on page 31 . 14 clkout output, cmos n/a 60mhz reference clock output. all ulpi signals are driven synchronous to the rising edge of this clock. 15 vdd1.8 power n/a 1.8v for digital circuitry on chip. supplied by on-chip regulator when reg_en is active. place a 0.1uf capacitor near this pin and connect the capacitor from this pin to ground. connect pin 15 to pin 26. 16 vdd3.3 power n/a a 0.1uf bypass capacitor should be connected between this pin and the ground plane on the pcb. table 3-1: USB3300 pin definitions 32-pin qfn package (continued) pin name direction, type active level description
? 2014-2015 microchip technology inc. ds00001783b-page 9 USB3300 17 data[7] i/o, cmos, pull-low n/a 8-bit bi-directional data bus. bus ownership is determined by dir. the link and phy initiate data transfers by driving a non-zero pattern onto the data bus. ulpi defines interface timing for a single-edge data transfers with respect to rising edge of clkout. data[7] is the msb and data[0] is the lsb. 18 data[6] i/o, cmos, pull-low n/a 19 data[5] i/o, cmos, pull-low n/a 20 data[4] i/o, cmos, pull-low n/a 21 data[3] i/o, cmos, pull-low n/a 22 data[2] i/o, cmos, pull-low n/a 23 data[1] i/o, cmos, pull-low n/a 24 data[0] i/o, cmos, pull-low n/a 25 vdd3.3 power n/a a 0.1uf bypass capacitor should be connected between this pin and the ground plane on the pcb. 26 vdd1.8 power n/a 1.8v for digital circuitry on chip. supplied by on-chip regulator when reg_en is active. when using the internal regulators, place a 4.7uf low-esr capacitor near this pin and connect the capacitor from this pin to ground. connect pin 26 to pin 15. do not connect vdd1.8 to vdda1.8 when using internal regulators. when the regulators are disabled, pin 29 may be connected to pins 26 and 15. 27 xo output, analog n/a crystal pin. if using an external clock on xi this pin should be floated. 28 xi input, analog n/a crystal pin. a 24mhz crystal is supported. the crystal is placed across xi and xo. an external 24mhz clock source may be driven into xi in place of a crystal. 29 vdda1.8 power n/a 1.8v for analog circuitry on chip. supplied by on-chip regulator when reg_en is active. place a 0.1uf capacitor near this pin and connect the capacitor from this pin to ground. when using the internal regulators, place a 4.7uf low-esr capacitor near this pin in parallel with the 0.1uf capacitor. do not connect vdd1.8a to vdd1.8 when using internal regulators. when the regulators are disabled, pin 29 may be connected to pins 26 and 15. 30 vdd3.3 power n/a analog 3.3 volt supply. a 0.1uf low esr bypass capacitor connected to the ground plane of the pcb is recommended. table 3-1: USB3300 pin definitions 32-pin qfn package (continued) pin name direction, type active level description
USB3300 ds00001783b-page 10 ? 2014-2015 microchip technology inc. 31 reg_en i/o, cmos, pull-low n/a on-chip 1.8v regulator enable. connect to ground to disable both of the on chip (vdda1.8 and vdd1.8) regulators. when regulators are disabled: ? external 1.8v must be supplied to vdda1.8 and vdd1.8 pins. when the regulators are disabled, vdda1.8 may be connected to vdd1.8 and a bypass capacitor (0.1uf recommended) should be connected to each pin. ? the voltage at vdd3.3 must be at least 2.64v (0.8 * 3.3v) before voltage is applied to vdda1.8 and vdd1.8. 32 rbias analog, cmos n/a external 12k ? +/- 1% bias resistor to ground. gnd flag ground n/a ground. the flag must be connected to the ground plane with a via array under the exposed flag. this is the main ground for the ic. table 3-1: USB3300 pin definitions 32-pin qfn package (continued) pin name direction, type active level description
? 2014-2015 microchip technology inc. ds00001783b-page 11 USB3300 4.0 operational description table 4-1: maximum guaranteed ratings parameter symbol condi tion min typ max units maximum vbus, id, extvbus, dp, and dm voltage to gnd v max_5v -0.5 +5.5 v maximum vdd1.8 and vdda1.8 voltage to ground v max_1.8v -0.5 2.5 v maximum 3.3v supply voltage to ground v max_3.3v -0.5 4.0 v maximum i/o voltage to ground v max_in -0.5 4.0 v operating temperature t max_op -40 85 c storage temperature t max_stg -55 150 c esd performance all pins v hbm human body model 8 kv latch-up performance all pins i ltch_up eia/jesd 78, class ii 150 ma note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4-2: recommended operating conditions parameter symbol condi tion min typ max units vdd3.3 to gnd v dd3.3 3.0 3.3 3.6 v input voltage on digital pins v i 0.0 v dd3.3 v voltage on analog i/o pins (dp, dm, id) v i(i/o) 0.0 v dd3.3 v vbus to gnd v vbus 0.0 5.25 ambient temperature t a -40 85 c
USB3300 ds00001783b-page 12 ? 2014-2015 microchip technology inc. 5.0 electrical characteristics table 5-1: electrical characteristics: supply pins parameter symbol condi tion min typ max units unconfigured current i avg(ucfg) device unconfigured same as idle ma fs idle 3.3v current i avg(fs33) fs idle not data transfer 18.8 21.9 ma fs idle 1.8v current i avg(fs18) fs idle not data transfer 36.4 43.2 ma fs transmit 3.3v current i avg(fstx33) fs current during data transmit 36.0 41.6 ma fs transmit 1.8v current i avg(fstx18) fs current during data transmit 36.8 43.2 ma fs receive 3.3v current i avg(fsrx33) fs current during data receive 22.5 27.0 ma fs receive 1.8v current i avg(fsrx18) fs current during data receive 36.7 43.4 ma hs idle 3.3v current i avg(hs33) hs idle not data transfer 22.1 25.4 ma hs idle 1.8v current i avg(hs18) hs idle not data transfer 38.7 45.6 ma hs transmit 3.3v current i avg(hstx33) hs current during data transmit 25.4 29.0 ma hs transmit 1.8v current i avg(hstx18) hs current during data transmit 39.1 46.2 ma hs receive 3.3v current i avg(hsrx33) hs current during data receive 23.0 26.6 ma hs receive 1.8v current i avg(hsrx18) hs current during data receive 39.6 46.8 ma low power mode 3.3v current i dd(lpm33) vbus 15k ? pull-down and 1.5k ? pull-up resistor currents not included. 59.4 ua low power mode 1.8v current i dd(lpm18) vbus 15k ? pull-down and 1.5k ? pull-up resistor currents not included. 25.5 ua note: ?v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = -40c to +85c; unless otherwise specified. ? sessend and vbusvld comparators disabled. interface protection disabled. ? maximum current numbers are worst case ov er supply voltage, temperature and process. table 5-2: electrical characteristics: clkout start-up parameter symbol condition min typ max units suspend recovery time t start 2.25 3.5 ms note: the usb330 uses the autoresume feature, section 6.3 , for host start-up of less than 1ms. table 5-3: dc electrical ch aracteristics: logic pins parameter symbol condition min typ max units low-level input voltage v il v ss 0.8 v high-level input voltage v ih 2.0 v dd3.3 v low-level output voltage v ol i ol = 8ma 0.4 v high-level output voltage v oh i oh = -8ma v dd3.3 - 0.4 v input leakage current i li 10 ua pin capacitance cpin 4 pf note: v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = -40c to +85c; unless otherwise specified.
? 2014-2015 microchip technology inc. ds00001783b-page 13 USB3300 table 5-4: dc electrical characterist ics: analog i/o pins (dp/dm) parameter symbol condition min typ max units fs functionality input levels differential receiver input sensitivity v difs | v(dp) - v(dm) | 0.2 v differential receiver common-mode voltage v cmfs 0.8 2.5 v single-ended receiver low level input voltage v ilse 0.8 v single-ended receiver high level input voltage v ihse 2.0 v single-ended receiver hysteresis v hysse 0.050 0.150 v output levels low level output voltage v fsol pull-up resistor on dp; r l = 1.5k ? to v dd3.3 0.3 v high level output voltage v fsoh pull-down resistor on dp, dm; r l = 15k ? to gnd 2.8 3.6 v termination driver output impedance for hs and fs z hsdrv steady state drive 40.5 45 49.5 input impedance z inp tx, rpu disabled 1.0 m ? pull-up resistor impedance z pu bus idle 0.900 1.24 1.575 k ? pull-up resistor impedance z purx device receiving 1.425 2.26 3.09 k ? pull-dn resistor impedance z pd 14.25 15.0 15.75 k ? hs functionality input levels hs differential in put sensitivity v dihs | v(dp) - v(dm) | 100 mv hs data signaling common mode voltage range v cmhs -50 500 mv hs squelch detection threshold (differential) v hssq squelch threshold 100 mv un-squelch threshold 150 mv output levels hi-speed low level output voltage (dp/dm referenced to gnd) v hsol 45 ? load -10 10 mv hi-speed high level output voltage (dp/dm referenced to gnd) v hsoh 45 ? load 360 440 mv hi-speed idle level output voltage (dp/dm referenced to gnd) v olhs 45 ? load -10 10 mv chirp-j output voltage (differential) v chirpj hs termination resistor disabled, pull-up resistor connected. 45 ? load. 700 1100 mv chirp-k output voltage (differential) v chirpk hs termination resistor disabled, pull-up resistor connected. 45 ? load. -900 -500 mv
USB3300 ds00001783b-page 14 ? 2014-2015 microchip technology inc. leakage current off-state leakage current i lz 10 ua port capacitance transceiver input capacitance c in pin to gnd 5 10 pf note: v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = -40c to +85c; unless otherwise specified. table 5-5: dynamic characteristics: analog i/o pins (dp/dm) parameter symbol condi tion min typ max units fs output driver timing rise time t fsr c l = 50pf; 10 to 90% of |v oh - v ol | 420ns fall time t fff c l = 50pf; 10 to 90% of |v oh - v ol | 420ns output signal crossover voltage v crs excluding the first transition from idle state 1.3 2.0 v differential rise/fall time matching frfm excluding the first transition from idle state 90 111.1 % hs output driver timing differential rise time t hsr 500 ps differential fall time t hsf 500 ps driver waveform requirements eye pattern of template 1 in usb 2.0 specification hi-speed mode timing receiver waveform requirements eye pattern of template 4 in usb 2.0 specification data source jitter and receiver jitter tolerance eye pattern of template 4 in usb 2.0 specification note: v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = -40c to +85c; unless otherwise specified. table 5-6: otg electrical characteristics parameter symbol condition min typ max units sessend trip point v sessend 0.2 0.5 0.8 v sessvld trip point v sessvld 0.8 1.4 2.0 v vbusvld trip point v vbusvld 4.4 4.58 4.75 v vbus pull-up r vbuspu vbus to vdd3.3 ( chargevbus = 1) 281 340 vbus pull-down r vbuspd vbus to gnd ( dischargevbus = 1) 656 850 vbus impedance r vbus vbus to gnd 40 75 100 k ? id pull-up resistance r idpullup idpullup = 1 80 100 120 k ? id pull-up resistance r id idpullup = 0 1 m ? stp pull-up resistance r stp interfaceprotectdisable = 0 240 330 600 k ? note: v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = -40c to +85c; unless otherwise specified. table 5-4: dc electrical characteristics: analog i/o pins (dp/dm) (continued) parameter symbol condition min typ max units
? 2014-2015 microchip technology inc. ds00001783b-page 15 USB3300 5.1 piezoelectric resonator for internal oscillator the internal oscillator may be used with an external quartz crystal or ceramic resonator as described in section 6.3 . see table 5-8 for the recommended crystal specifications. see table 5-1 for the ceramic resonator part number for commer- cial temperature applications. at this ti me, the ceramic resonator does not offer su fficient temperature stability to operate over the industrial temperature range. note 5-1 the required bit rate accuracy for hi-speed usb app lications is 500 ppm as provided in the usb 2.0 specification. this takes into account th e effect of voltage, temperature, aging, etc. note 5-2 0 o c for commercial applications, -40 o c for industrial applications. note 5-3 +70 o c for commercial applications, +85 o c for industrial applications. note 5-4 this number includes the pad, the bond wire and the lead frame. printed circuit board (pcb) capacitance is not included in this value. the pcb capacitance value and the capacitance value of the xo and xi pins are required to accurately calculate th e value of the two external load capacitors. note 5-5 this is a generic part number assigned by mura ta. the oscillating frequency is affected by stray capacitance on the printed circuit board (pcb). murata will assign the final part number for each customer?s pcb after characterizing the customer?s pcb design. table 5-7: regulator output voltages parameter symbol condition min typ max units v dda1.8 v dda1.8 normal operation ( suspendm = 1) 1.6 1.8 2.0 v v dda1.8 v dda1.8 low power mode ( suspendm = 0) 0v v dd1.8 v dd1.8 1.6 1.8 2.0 v note: v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = -040c to +85c; unless otherwise specified. table 5-8: USB3300 quartz crystal specifications parameter symbol condition min typ max units crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund -24-mhz total allowable ppm budget - - 500 ppm note 5-1 shunt capacitance c o -7 typ-pf load capacitance c l - 20 typ - pf drive level p w 0.5 - - mw equivalent series resistance r 1 --30ohm operating temperature range note 5-2 - note 5-3 o c USB3300 xi pin capacitance - 3 typ - pf note 5-4 USB3300 xo pin capacitance - 3 typ - pf note 5-4 table 5-1: USB3300 ceramic resonator part number frequency murata part number notes 24 mhz cstce24m0xk1***-r0 commercial temp only, note 5-5
USB3300 ds00001783b-page 16 ? 2014-2015 microchip technology inc. 6.0 architecture overview the USB3300 architecture can be broken down into the following blocks shown in figure 6-1, "simplified USB3300 architecture" below. 6.1 ulpi digital the USB3300 uses the industry standard ulpi digital inte rface to facilitate communication between the phy and link (device controller). the ulpi interface is designed to reduce the number of pi ns required to connect a discrete usb phy to an asic or digital controller. for example, a full utmi+ level 3 otg interface requires 54 signals while a ulpi interface requires only 12 signals. the ulpi interface is documented completely in the ?utmi+ low pin interface (ulpi) specification? document (www.ulpi.org). the following sections highlight the key oper ating modes of the USB3300 digital interface. 6.1.1 overview figure 6-2 illustrates the block diagram of the ulpi digital functi ons. it should be noted t hat this phy does not use a ?ulpi wrapper? around a utmi+ phy core as the ulpi specification implies. the advantage of a ?wrapper less? architecture is that th e phy has a lower usb latency than a design which must first register signals into the phy?s wrapper before the transfer to the phy core. a low latency phy allows a link to use a wrapper around a utmi link and still make the required usb tu rn-around timing given in the usb 2.0 specification. figure 6-1: simplified USB3300 architecture ulpi digital otg module data[7:0] internal regulator & por bias gen. clkout nxt dir stp vdd3.3 xtal & pll xi cpen vbus id vdd3.3 dp dm USB3300 vdd1.8 vdda1.8 xo rbias extvbus hs xcvr fs/ls xcvr resistors rpu_dp rpd_dm rpd_dp rpu_dm
? 2014-2015 microchip technology inc. ds00001783b-page 17 USB3300 rxenddelay maximum allowed by the ut mi+/ulpi for 8-bit data is 63 high spee d clocks. USB3300 uses a low latency high speed receiver path to lower the rxenddelay to 43 high speed clocks. this low latency design gives the link more cycles to make decisions and reduces the link complexity. this is the result of the ?wrapper less? architecture of the USB3300. this low rxenddelay should allow legacy utmi li nks to use a ?wrapper? to convert the utmi+ interface to a ulpi interface. in figure 6-2, "ulpi digital block diagram" , a single ulpi protocol block decodes the ulpi 8-bit bi-directional bus when the link addresses the phy. the link must use the dir ou tput to determine direction of the ulpi data bus. the USB3300 is the ?bus arbitrator?. the ulpi protocol block will route data/commands to the transmitter or the ulpi reg- ister array. figure 6-2: ulpi di gital block diagram data[7:0] interrupt control high speed tx full speed tx low speed tx high speed data recovery full / low speed data recovery ulpi protocol block 6pinserial mode xcvrselect[1:0] termselect opmode[1:0] reset suspendm 3pinserial mode clocksuspendm autoresume indicator complement indicator pass thru interface protect disable idpullup dppulldown dmpulldown dischrgvbus chrgvbus drvvbus drvvbusexternal useexternal vbus indicator interruptenable rise[4:0] interruptenablefall[4:0] interruptstatus[4:0] interruptlatch[4:0] linestates[1:0] vbusvalid sessionvalid sessionend hs tx data fs/ls tx data hs rx data fs/ls data note: the USB3300 uses a wrapperless ulpi interface. dir nxt stp tx data rx data por ulpi register array hostdisconnect idgnd to otg module transceiver control module to usb transceiver from otg module to usb transceiver rxd cmd from usb transceiver
USB3300 ds00001783b-page 18 ? 2014-2015 microchip technology inc. 6.1.2 ulpi interface signals utmi+ low pin interface (ulpi) uses 12-pins to connect a fu ll otg host / device phy to an soc. a reduction of exter- nal pins on the phy is accomplished by realizing that many of the relatively static config uration pins (xcvrselect[1:0], termselect, opmode[1:0], and dppulldown dmpulldown to list a few,) can be implemented by having a internal static register array. an 8-bit bi-directional data bus clocked at 60mhz allows the link to access this internal register array and transfer usb packets to and from the phy. the remaining 3 pins function to control the data flow and arbitrate the data bus. direction of the 8-bit data bus is contro l by the dir output from t he phy. another output nxt is used to control data flow into and out of the device. finally, stp, which is in i nput to the phy, terminates transfers and is used to start up and resume from a suspend state. the 12 signals are described below in table 6-1, "ulpi interface signals" . USB3300 implements a single data rate (sdr) ulpi in terface with all data transfers happening on the rising edge of the clkout. clkout is supplied by the phy. the ulpi interface supports the two basic modes of oper ation, synchronous mode and low power mode. synchronous mode with the signals all changing relative to the 60mhz clockout. low power mode where the clock is off in a sus- pended state and the lower two bits of the data bus contai n the linestate[1:0] signals. ulpi adds to low power mode, an interrupt output which permits the link to receive an asynchronous interrupt when the otg comparators, or id pin change state. in synchronous mode operation, data is transferred on the rising edge of clkout . direction of the data bus is deter- mined by the state of dir. when dir is high, the phy is driving data[7:0]. when dir is low, the link is driving data[7:0]. each time dir changes, a ?turn-around? cycle occurs where neither the link nor phy drive the data bus for one clock cycle. during the ?turn?around? cycle, the state of da ta[7:0] is unknown and the phy will not read the data bus. because usb uses a bit-stuffing encodi ng, some means of allowing the phy to throttle the usb transmit data is needed. the ulpi signal nxt is used to request the next byte to be placed on the databus by the link layer. table 6-1: ulpi interface signals signal direction description clkout out 60mhz reference clock output. all ulpi signals are driven synchronous to the rising edge of this clock. data[7:0] i/o 8-bit bi-directional data bus. bus ow nership is determined by dir. the link and phy initiate data transfers by driving a non-zer o pattern onto the data bus. ulpi defines interface timing for a single-edge data transfers with respect to rising edge of clkout. dir out controls the direction of the data bus. when the phy has data to transfer to the link, it drives dir high to take ownershi p of the bus. when the phy has no data to transfer it drives dir low and monitors the bus for commands from the link. the phy will pull dir high whenever the interf ace cannot accept data from the link, such as during pll start-up. stp in the link asserts stp for one clock cy cle to stop the data stream currently on the bus. if the link is sending data to the phy, stp indicates the last byte of data was on the bus in the previous cycle. nxt out the phy asserts nxt to throttle the data. when the link is sending data to the phy, nxt indicates when the current byte has been accepted by the phy. the link places the next byte on the data bus in th e following clock cycle.
? 2014-2015 microchip technology inc. ds00001783b-page 19 USB3300 6.1.3 ulpi interface timing the control and data timing relationships are given in figure 6-3, "ulpi timing diagram" and table 6-2, "ulpi interface timing" . the usb300 phy provides clkout and all timing is relative to the rising clock edge. the timing relationships detailed below apply to synchronous mode only. 6.1.4 ulpi register array the USB3300 phy implements all of the ulpi registers deta iled in the ulpi revision 1.1 specification. the complete USB3300 ulpi register set is shown in table 6-3, "ulpi register map" . all registers are 8 bits. this table also includes the default states of the regi ster upon por. the reset bit in the function contro l register does no t reset the bits of the ulpi register array. the link should not read or write to any registers not listed in this table. figure 6-3: ulpi timing diagram table 6-2: ulpi interface timing parameter symbol min max units setup time (control in, 8-bit data in) t sc ,t sd 5.0 ns hold time (control in, 8-bit data in) t hc , t hd 0ns output delay (control out, 8-bit data out) t dc , t dd 2.0 5.0 ns note: v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = -40c to 85c; unless otherwise specified. clock out - clkout control in - stp data in - data[7:0] control out - dir, nxt data out - data[7:0] t sc t sd t hc t hd t dc t dc t dd
USB3300 ds00001783b-page 20 ? 2014-2015 microchip technology inc. 6.1.4.1 vendor id low: address = 00h (read only) 6.1.4.2 vendor id high: address = 01h (read only) 6.1.4.3 product id low: address = 02h (read only) 6.1.4.4 vendor id low: address = 03h (read only) table 6-3: ulpi register map register name default state address (6bit) read write set clear vendor id low 24h 00h - - - vendor id high 04h 01h - - - product id low 04h 02h - - - product id high 00h 03h - - - function control 41h 04-06h 04h 05h 06h interface control 00h 07-09h 07h 08h 09h otg control 06h 0a-0ch 0ah 0bh 0ch usb interrupt enable rising 1fh 0d-0fh 0dh 0eh 0fh usb interrupt enable falling 1fh 10-12h 10h 11h 12h usb interrupt status 00h 13h - - - usb interrupt latch 00h 14h - - - debug 00h 15h - - - scratch register 00h 16-18h 16h 17h 18h field name bit default description vendor id low 7:0 24h microchip vendor id field name bit default description vendor id high 7:0 04h microchip vendor id field name bit default description product id low 7:0 04h microchip product id revision a0 field name bit default description product id high 7:0 00h microchip product id revision a0
? 2014-2015 microchip technology inc. ds00001783b-page 21 USB3300 6.1.4.5 function control: address = 04-06h (r ead), 04h (write), 05h (set), 06h (clear) 6.1.4.6 interface control: address = 07-09h (read), 07h (write), 08h (set), 09h (clear) field name bit default description xcvrselect[1:0] 1:0 01b selects the required transceiver speed. 00b: enables hs transceiver 01b: enables fs transceiver 10b: enables ls transceiver 11b: enables fs transceiver for ls packets (fs preamble automatically pre-pended) termselect 2 0b controls the dp and dm termination depending on xcvrselect, opmode, dppulldown, and dmpulldown. the dp and dm termination is detailed in table 6-8, "dp/dm termination vs. signaling mode" . opmode 4:3 00b selects the required bit encoding style during transmit. 00b: normal operation 01b: non-driving 10b: disable bit-stuff and nrzi encoding 11b: reserved reset 5 0b active high transceiver reset. this reset does not reset the ulpi interface or register set. automatically clears after reset is complete. suspendm 6 1b active low phy suspend. when cleared the phy will enter low power mode as detailed in section 6.1.9, "low power mode" . automatically set when exiting low power mode. reserved 7 0b driven low. field name bit default description 6-pin fslsserialmode 0 0b changes the ulpi inte rface to a 6-pin serial mode. the phy will automatically clear this bit when exiting serial mode. 3-pin fslsserialmode 1 0b changes the ulpi inte rface to a 3-pin serial mode. the phy will automatically clear this bit when exiting serial mode. reserved 2 0b driven low. clocksuspendm 3 0b enables link to turn on 60mhz clkout in serial mode. 0b: disable clock in serial mode. 1b: enable clock in serial mode. autoresume 4 0b only applicable in host mode. enables the phy to automatically transmit resume signaling. this function is detailed in section 6.1.7.4, "host resume k" . indicatorcomplement 5 0b inverts the extvbus signal. this function is detailed in section 6.5.4, "external vbus indicator" . indicatorpassthru 6 0b disables anding the internal vbus comparator with the extvbus input when asserted. this function is detailed in section 6.5.4 . interfaceprotectdisable 7 0b used to disable the integrated stp pull-up resistor used for interface protection. this function is detailed in section 6.1.9.3, "interface protection" .
USB3300 ds00001783b-page 22 ? 2014-2015 microchip technology inc. 6.1.4.7 otg control: address = 0a-0ch (read), 0ah (write), 0bh (set), 0ch (clear) 6.1.4.8 usb interrupt enable rising: address = 0d-0fh (read), 0dh (write), 0eh (set), 0fh (clear) field name bit default description idpullup 0 0b connects a pull-up resistor from the id pin to vdd3.3 0b: disables the pull-up resistor 1b: enables the pull-up resistor dppulldown 1 1b enables the 15k ohm pull-down resistor on dp. 0b: pull-down resistor not connected to dp 1b: pull-down resistor connected to dp dmpulldown 2 1b enables the 15k ohm pull-down resistor on dm. 0b: pull-down resistor not connected to dm 1b: pull-down resistor connected to dm dischrgvbus 3 0b this bit is only used during srp. connects a resistor from vbus to ground to discharge vbus. 0b: disconnect resistor from vbus to ground 1b: connect resistor from vbus to ground chrgvbus 4 0b this bit is only used during srp. connects a resistor from vbus to vdd3.3 to charge vbus above the sessvalid threshold. 0b: disconnect resistor from vbus to vdd3.3 1b: connect resistor from vbus to vdd3.3 drvvbus 5 0b used to enable external 5 volt supply to drive 5 volts on vbus. this signal is or?ed with drvvbusexternal. 0b: do not drive vbus 1b: drive vbus drvvbusexternal 6 0b used to enable external 5 volt supply to drive 5 volts on vbus. this signal is or?ed with drvvbus. 0b: do not drive vbus 1b: drive vbus useexternalvbus indicator 7 0b tells the phy to use an external vbus over-current or voltage indicator. this function is detailed in section 6.5.4, "external vbus indicator" . 0b: use the internal vbusvalid comparator 1b: use the extvbus input as for vbusvalid signal. field name bit default description hostdisconnect rise 0 1b generate an interrupt event notification when hostdisconnect changes from low to high. applicable only in host mode. vbusvalid rise 1 1b generate an interrupt event notification when vbusvalid changes from low to high. sessvalid rise 2 1b generate an interrupt ev ent notification when sessvalid changes from low to high. sessend rise 3 1b generate an interrupt event notification when sessend changes from low to high. idgnd rise 4 1b generate an interrupt event notification when idgnd changes from low to high. reserved 7:5 0h driven low.
? 2014-2015 microchip technology inc. ds00001783b-page 23 USB3300 6.1.4.9 usb interrupt enable falling: address = 10-12 h (read), 10h (w rite), 11h (set), 12h (clear) 6.1.4.10 usb interrupt status register: address = 13h (read only with auto clear) 6.1.4.11 usb interrupt status: address = 14h (read only with auto clear) field name bit default description hostdisconnect fall 0 1b generate an interrupt event notification when hostdisconnect changes from high to low. applicable only in host mode. vbusvalid fall 1 1b generate an interrupt event notification when vbusvalid changes from high to low. sessvalid fall 2 1b generate an interrupt ev ent notification when sessvalid changes from high to low. sessend fall 3 1b generate an interrupt event notification when sessend changes from high to low. idgnd fall 4 1b generate an interrupt event notification when idgnd changes from high to low. reserved 7:5 0h driven low. field name bit default description hostdisconnect 0 0b current value of the utmi+ hostdisconnect output. applicable only in host mode. vbusvalid 1 0b current value of the utmi+ vbusvalid output. sessvalid 2 0b current value of the utmi+ sessvalid output. sessend 3 0b current value of the utmi+ sessend output. idgnd 4 0b current value of the utmi+ idgnd output. reserved 7:5 0h driven low. field name bit default description hostdisconnect latch 0 0b set to 1b by t he phy when an unmasked event occurs on hostdisconnect. cleared when this register is read. applicable only in host mode. vbusvalid latch 1 0b set to 1b by the phy when an unmasked event occurs on vbusvalid. cleared when this register is read. sessvalid latch 2 0b set to 1b by the phy when an unmasked event occurs on sessvalid. cleared when this register is read. sessend latch 3 0b set to 1b by the phy when an unmasked event occurs on sessend. cleared when this register is read. idgnd latch 4 0b set to 1b by the phy when an unmasked event occurs on idgnd. cleared when this register is read. reserved 7:5 0h driven low.
USB3300 ds00001783b-page 24 ? 2014-2015 microchip technology inc. 6.1.4.12 debug register: address = 15h (read only) 6.1.4.13 scratch register: address = 16-18h (read), 16h (write), 17h (set), 18h (clear) 6.1.4.14 carkit register access the carkit registers are reserved for microchip testin g and should not be written to or read by the link. 6.1.4.15 extended register access the extended registers are reserved for microchip testing and should not be written to or read by the link. 6.1.4.16 vendor register access the vendor specific registers are reserved for microchip testing and should not be written to or read by the link. the vendor specific registers include the range from 30h to 3fh. 6.1.5 ulpi register access a command from the link begins a ulpi transfer from the link to the USB3300. anytime the link wants to write or read a ulpi register, the link will need to wait until dir is low, and then send a transmit command byte (txd cmd) to the phy. the txd cmd byte informs the phy of the type of data being sent. the txd cmd is followed by the a data transfer to or from the phy. table 6-4, "ulpi txd cmd byte encoding" gives the txd command byte (txd cmd) encoding for the USB3300. the upper two bits of the tx cmd instruct the phy as to what type of packet the link is transmitting. field name bit default description linestate0 0 0b contains the current value of linestate[0]. linestate1 1 0b contains the current value of linestate[1]. reserved 7:2 000000b driven low. field name bit default description scratch 7:0 00h empty register byte for test ing purposes. software can read, write, set, and clear this register and the phy functionality will not be affected. table 6-4: ulpi txd cmd byte encoding command name cmd bits[7:6] cmd bits[5:0] command description idle 00b 000000b ulpi idle transmit 01b 000000b usb transmit packet with no packet identifier (nopid) 00xxxxb usb transmit packet identifier (pid) where data[3:0] is equal to the 4-bit pid. p 3 p 2 p 1 p 0 where p 3 is the msb. register write 10b xxxxxxb immediate register write command where data[5:0] = 6-bit register address register read 11b xxxxxxb immediate register read command where data[5:0] = 6-bit register address
? 2014-2015 microchip technology inc. ds00001783b-page 25 USB3300 6.1.5.1 ulpi register write a ulpi register write operation is given in figure 6-4 . the txd command with a register write data[7:6] = 10b is driven by the link at t0. the register address is encoded into data[5:0] of the txd cmd byte. to write to a register, the link will wait until dir is low, and at t0, drive the txd cmd on the databus. at t2 the phy will drive nxt high. on the next rising clock edge, t3, the li nk will write the register data. at t4 the phy will accept the register data and the link will drive an idle on the bus and drive stp high to signal the end of the data packet. finally, at t5, the phy will latch the data into the register and drive nxt low. the link will pull stp low. nxt is used to control when the link drives the register data on the bus. dir is low throughout this transaction since the phy is receiving data from the link. stp is used to end the transaction and data is r egistered after the de-assertion of stp. after the write operation completes, the link must drive a ulpi idle (00h) on the data bus or the USB3300 may decode the bus value as a ulpi command. figure 6-4: ulpi register write dir clk data[7:0] stp nxt txd cmd (reg write) idle reg data[n] idle ulpi register reg data [n-1] reg data [n] t0 t1 t2 t3 t5 t4 t6
USB3300 ds00001783b-page 26 ? 2014-2015 microchip technology inc. 6.1.5.2 ulpi register read a ulpi register read operation is given in figure 6-5 . the link drives a txd cmd byte with data[7:6] = 11h for a reg- ister read. data[5:0] of the ulpi txd co mmand bye contain the register address. at t0, the link will place the txd cmd on the databus. at t2, the phy will bring nxt high, si gnaling that the link it is ready to accept the data transfer. at t3, the phy reads the txd cmd, determines it is a register read, and asserts dir to gain control of the bus. the phy will also de-assert nxt. at t4, the bus ownership has transferred back to the phy and the phy drives the requested register onto the databus. at t5, the link will read the databus and the phy will drop dir low returning control of the bus back to the link. after the turn around cycle, the link must drive a ulpi idle com- mand at t6. 6.1.6 ulpi rxd cmd the link needs several more important states of information wh ich were provided by the lines tate[1:0], rxactive, rxvalid and rxerror. when an implementing the otg functions the vbus and id pin states must also be transferred into the link. ulpi defines a receive command byte (r xd cmd) that contains this informa tion. the encoding of the rxd cmd byte is given in the table 6-5, "ulpi rx cmd encoding" . transfer of the rxd cmd byte occurs when in synchronous mode when the phy has control of the bus. transfers of the rxd cmd occur after: a transmit cmd has issued stp, a linestate change when not transmitting, a usb receive, or an interrupt event occurs. in figure 6-2, "ulpi digital block diagram" , the ulpi protocol block determines when to send an rxd cmd. when a linestate change occurs the rxd cmd is se nt immediately if t he dir output is low. when a usb receive is occurring rxd cmds are sent when ever nxt = 0 and dir = 1. when a usb transmit occurs the rxd cmds are returned to the link after the stp is asserted ending the link to USB3300 transfer of the bytes to be sent on the transmit. to summarize a rxd cmd transfer occurs: ? when dir is low and a linestate change occurs. ? when vbus and/or id comparators change state. ? during a usb receive when nxt is low. ? after stp is asserted during a usb transmit cmd. figure 6-5: ulpi register read dir clk data[7:0] stp nxt txd cmd reg read idle t0 reg data turn around turn around t1 t2 t3 t4 t5 t6 idle
? 2014-2015 microchip technology inc. ds00001783b-page 27 USB3300 note 1: an ?x? is a do not care and can be either a logic 0 or 1. 2: the value of vbusvalid is defined in table 6-10, "external vbus indicator logic" . 6.1.7 USB3300 transmitter the USB3300 ulpi transmitter fully suppor ts hs, fs, and ls transmit operations. figure 6-2, "ulpi digital block dia- gram" shows the high speed, full speed, and low speed transmitt er block controlled by ulpi protocol block. encoding of the usb packet follows the bit-stuffing and nrzi outlined in the usb 2.0 specification. many of these functions are re-used between the high speed and full/low speed transmitters. when using the USB3300, table 6-8, "dp/dm termi- nation vs. signaling mode" should always be used as a guideline on how to configure for various modes of operation. the transmitter decodes the inputs of xcvrselect, termselect, opmodes, dppulldown and dmpulldown to determine what operation is expected. users must strictly adhere to the modes of operation given in ta b l e 6 - 8 . several important functions for a device and host are designed in the transmitter blocks. the USB3300 transmitter will transmit a 32-bit long high sp eed synch before every high speed packet. in full and low speed modes a 8-bit synch is transmitted. when the device or host needs to chirp for high speed port negotiation, the opmode bits=10 will turn off the bit-stuffing and nrzi encoding in the transmitter. at the end of a chirp, the USB3300 opmode register bits should be changed only after the rxcmd linestate encoding indicates that the tran smitter has completed transmitting. should the opmode be switched to normal bit-stuffing and nrzi encoding before th e transmit pipeline is empty, the remaining data in the pipe- line may be transmitted in an bit-stuff encoding format. please refer to the ulpi specification for a detailed discussion of usb reset and hs chirp. 6.1.7.1 high speed long eop when operating as a hi-speed host, the USB3300 will automatically generate a 40 bit long end of packet (eop) after a sof pid (a5h). the USB3300 determines when to send the 40-bit long eop by decoding the ulpi txd cmd bits [3:0] for the sof. the 40-bit long eop is only transmitted when the dppulldown and dmpulldown bits are asserted. the hi-speed 40-bit long eop is used to detect a disconnect in high speed mode. in device mode, the USB3300 will not send a long eop after a sof pid. table 6-5: ulpi rx cmd encoding data [7:0] name description and value [1:0] linestate utmi linestate signals data[1] = linestate[1] data[0] = linestate[0] [3:2] encoded vbus state encoded vbus voltage states value vbus voltage sessend sessvld vbusvld 2 00 v vbus < v sess_end 10 0 01 v sess_end < v vbus < v sess_vld 00 0 10 v sess_vld < v vbus < v vbus_vld x1 0 11 v vbus_vld < v vbus xx 1 [5:4] rx event encoding encoded utmi event signals value rxactive rxerror hostdisconnect 00 0 0 0 01 1 0 0 11 1 1 0 10 x x 1 [6] state of id pin set to the logic state of the id pin. a logic low indicates an a device. a logic high indicates a b device. [7] reserved always
USB3300 ds00001783b-page 28 ? 2014-2015 microchip technology inc. 6.1.7.2 low speed keep-alive low speed keep alive is supported by the USB3300. when in low speed (10b), the USB3300 will send out two low speed bit times of se0 when a sof pid is received. 6.1.7.3 utmi+ level 3 pre-amble is supported for utmi+ level 3 compatibility. when xcvrselect is set to (11b) in host mode, (dppulldown and dmpulldown both asserted) the USB3300 will pre-pend a full speed pre-amble before the lo w speed packet. full speed rise and fall times are used in this mode. the pre-amble co nsists of the following: full speed sync, the encoded pre-pid (c3h) and then full speed idle (dp=1 and dm = 0). a low speed packet follows with a sync, data and a ls eop. 6.1.7.4 host resume k resume k generation is supported by the USB3300. when the USB3300 exits the suspended low power state, the USB3300, when operating as a host, will transmit a k on dp /dm. the transmitters will end the k with se0 for two low speed bit times. if the USB3300 was operating in high spee d mode before the suspend, the host must change to high speed mode before the se0 ends. se0 is two low speed bit times which is about 1.2 us. the ulpi specification has an explicit discussion of t he resume sequence and the order of operations required. in device mode, the resume k will not append a se0 but releas e the dp/ dm lines to allow the pull up to return the bus to the correct idle state, depending upon the operational mode of the USB3300. refer to table 6-8, "dp/dm termination vs. signaling mode" . 6.1.7.5 no sync and eop generation (opmode 11) (optional) utmi+ defines an opmode 11 where no sync and eop generati on occurs in hi-speed operation. this is an option to the ulpi specification and not implemented in the USB3300. 6.1.7.6 typical usb transmit with ulpi figure 6-6, "ulpi transmit" shows a typical usb transmit sequence. a tran smit sequence starts by the link sending a txd cmd where data[7:6] = 01b, data[5:4] = 00b, and data [3:0] = pid. the tx cmd with the pid is followed by transmit data. form the time the data is clocked into the transmitter it will appear at dp and dm 11 high speed bit times later. this time is the hs_tx_start_delay. during transmit the phy will use nxt to control the rate of dat a flow into the phy. if the USB3300 pipeline is full or bit- stuffing causes the data pipeline to overfill nxt is de-asse rted and the link will hold the value on data until nxt is asserted. the usb transmit ends when the link asserts stp while nxt is asserted. (note that the link cannot assert stp with nxt de-asserted since the USB3300 is expecting to fetch another byte from the link in this state). figure 6-6: ulpi transmit data[ 7: 0] dp/ dm di r clk stp nxt txd cmd (usb tx) idle d0 d2 d3 idle se0 !squelch se0 turn around turn around rxd cmd d1
? 2014-2015 microchip technology inc. ds00001783b-page 29 USB3300 once, the USB3300 completes transmitting, the dp/dm lines re turn to idle and an rxd cmd is returned to the link so the inter-packet timers may be updated by linestate. in the case of full speed or low speed, once stp is a sserted each fs/ls bit transition will generate a rxd cmd since the bit times are relatively slow. 6.1.8 USB3300 receiver the USB3300 ulpi receiver fully supports hs, fs, and ls transmit operations. in all three modes the receiver detects the start of packet and synchronizes to the incoming data packet . in the ulpi protocol, a received packet has the priority and will immediately follow regist er reads and rxd cmd transfers. figure 6-7, "ulpi receive" shows a basic usb packet received by the USB3300 over the ulpi interface. in figure 6-7, "ulpi receive" the phy asserts dir to take control of the data bus from the link. the assertion of dir and nxt in the same cycle contains additional information t hat rxactive has been asserted. when nxt is de-asserted and dir is asserted, the rxd cmd data is transferred to the link. after the last by te of the usb receive packet is trans- ferred to the phy, the linestate will return to idle. the ulpi full speed receiver operates according to the utmi /ulpi specification. in the full speed case, the nxt signal will assert only when the data bus has a valid received data byte. when nxt is low with dir high, the rxd cmd is driven on the data bus. in full speed, the USB3300 will not issue a rxactive de-a ssertion in the rxd cmd until the dp/dm linestate transition to idle. this prevents the link from violating the two full speed bit times minimum turn around time. 6.1.8.1 disconnect detection a high speed host must detect a disconnect by sampling the transmitter outputs during the long eop transmitted during a sof packet. the USB3300 only looks for a high speed disconnect during the long eop where the period is long enough for the disconnect reflection to return to the host phy. when a high speed disconnect occurs the USB3300 will return a rxd cmd and set the host disconnect bit in the ulpi interrupt status register (address 13h). when in fs or ls modes, the link is expected to handle all disconnect detection. 6.1.9 low power mode low power mode is a power down state to save current w hen the usb session is suspended. the link controls when the phy is placed into or out of low power mode. in low power mode all of the circuits are powered down except the interface pins, full speed receiver, vbus comparators, and id comparator. figure 6-7: ulpi receive dir clk data[7:0] stp nxt rxd cmd idle turn around pid d1 rxd cmd d2 turn around
USB3300 ds00001783b-page 30 ? 2014-2015 microchip technology inc. 6.1.9.1 entering low power/suspend mode to enter low power mode, the li nk will write a 0 or clear the suspendm bit in the function control register. once this write is complete, the phy will assert dir high and after fi ve rising edges of clkout, drive the clock low. once the clock is stopped, the phy will enter a low power state to conserve current. while in low power mode, the data interface is redefined so that the link can monitor linestate and the vbus voltage. in low power mode data[3:0] are redefined as shown in table 6-6, "interface signal mapping during low power mode" . linestate[1:0] is the combinational ou tput of the full speed receivers. the ?int? or interrupt signal indicates an unmasked interrupt has occurred. when an unmasked interrupt or linestate change has occurred, the link is notified and can determine if it should wake-up the phy. an unmasked interrupt can be caused by the following comp arators changing state, vbusvld, sessvld, sessend, and idgnd. if any of these signals change state during low powe r mode and either their rising or falling edge interrupt is enabled, data[3] will assert. during low power mode, the v busvld and sessend comparators can have their interrupts masked to lower the suspend current. refer to section 6.1.9.4, "minimizing current in low power mode" . while in low power mode, the data bus is driven asynch ronously because all of the phy clocks are stopped during low power mode. figure 6-8: entering low power mode table 6-6: interface signal mapping during low power mode signal maps to direction description linestate[0] data[0] out combinatorial linestate[0 ] driven directly by fs analog receiver. linestate[1] data[1] out combinatorial linestate[1 ] driven directly by fs analog receiver. reserved data[2] out driven low int data[3] out active high interrupt indication. must be asserted whenever any unmasked interrupt occurs. reserved data[7:4] out driven low dir clk data[7:0] stp nxt txd cmd (reg write) idle reg data[n] idle t0 t1 t2 t3 t5 t4 t6 t10 turn around low power mode suspendm (ulpi register bit) ...
? 2014-2015 microchip technology inc. ds00001783b-page 31 USB3300 6.1.9.2 exiting low power mode to exit low power mode, the link will a ssert stp. upon the assertion of stp, the USB3300 will begin its start-up pro- cedure. after the phy start-up is complete, the phy will st art the clock on clkout and de-assert dir. once dir has been de-asserted, the link can de-assert stp when ready and start operating in synchronous mode. the phy will auto- matically set the suspendm bit to a 1 in the function control register. the time from t0 to t1 is given in table 5-2, ?electrical characteristics: clkout start-up,? on page 12 . should the link de-assert stp before dir is de-asserted, th e USB3300 will detect this as a false resume request and return to low power mode. this is detailed in section 3.9.4 of the ulpi 1.1 specification. 6.1.9.3 interface protection ulpi protocol assumes that both the link and phy will keep t he ulpi data bus driven by either the link when dir is low or the phy when dir is high. the only exception is when dir has changed state and a turn around cycle occurs for 1 clock period. in the design of a usb system, there ca n be cases where the link may not be driving the ulpi bus to a known state while dir is low. two examples where this can happen is because of a slow link start-up or a hardware reset. start up protection upon start-up, when the phy de-asserts dir, the link must be ready to receive commands and drive idle on the data bus. if the link is not ready to receive commands or drive id le, it must assert stp before dir is de-asserted. the link can then de-assert stp when it has completed its start-up. if the link doesn?t assert stp before it can receive com- mands, the phy may interpret the databus state as a tx cmd and transmit invalid data onto the usb bus, or make invalid register writes. a link should be designed to have the default por state of the stp output high and th e data bus tri-stated. the USB3300 has weak pull-downs on the data bus to pr event these inputs from floating when not driven. in some cases, a link may be software configured and not have control of its stp pin until after the phy has started. in this case, the USB3300 has an internal pull-up on the stp input pad which will pull stp high while the link?s stp output is tri-stated. the stp pull-up resistor is enabled on por and can be disabled by setting the interfaceprotectdis- able bit 7 of the interface control register. the stp pull-up resistor will pull-up the link?s stp input high until the link configures and drives stp high. once the link completes its start-up, stp can be synchronously driven low. figure 6-9: exiting low power mode dir clk data[7:0] stp nxt turn around low power mode data bus ignored (slow link) idle (fast link) idle t0 t1 t2 t3 t5 t4 slow link drives bus idle and stp low fast link drives bus idle and stp low ... note: not to scale
USB3300 ds00001783b-page 32 ? 2014-2015 microchip technology inc. a link design which drives stp high during por can disable the pull-up resistor on stp by setting interfaceprotect- disable bit to 1. a motivation for this is to reduce the suspend current. in low power mode, stp is held low, which would draw current through the pull-up resistor on stp. warm reset designers should also consider the case of a warm restar t of a link with a phy in low power mode. once the phy enters low power mode, dir is asserted and the clock is st opped. the USB3300 looks for stp to be asserted to re- start the clock and then resume normal synchronous operation. should the USB3300 be suspended in low power mode, and th e link receives a hardware reset, provision is made to allow the phy to recover from low power mode and start its clock. if the link asserts stp on reset, the phy will exit low power mode and start its clock. if the link does not assert stp on reset the interface prot ection pull-up can be used. when the link is reset, its stp output will tri-state and the pull-up resistor will pull stp high, signaling the phy to restart its clock. 6.1.9.4 minimizing current in low power mode in order to minimize the suspend current in low power mode, the otg comparators can be disabled to reduce suspend current. during suspend, the vbusvld and sessend compar ators are not needed and can be disabled using the usb interrupt enable rise and usb interrupt enable fall registers. by disabling the interrupt in both the rise and fall reg- isters, the sessend and vbusvld comparators are turned of f. when exiting suspend, the link should immediately re- enable the comparators if host or otg functionality is needed. in addition to disabling the otg comparators in suspend, th e link may choose to disable the interface protect circuit. by setting the interface control, bit 7, interfaceprotectdisable high, the link can disable the pull-up resistor on stp. 6.1.10 full speed/low speed serial modes the USB3300 includes two serial modes to support legacy lin ks which use either the 3pin or 6pin serial format. to enter either serial mode, the link will need to write a 1 to the 6-pin fslsserialmode or the 3-pin fslsserialmode bit in the interface control register. the 6-pin serial mode is prov ided for legacy link designs and is not recommended for new designs. the serial modes are entered in the same manner as the en try into low power mode. the link writes the interface control register bit for the specific serial mode. the USB3300 will assert dir and shut off the clock after at least five clock cycles. then the data bus goes to the format of the serial mode selected. by default, the phy will shut off the 60mhz clock to conser ve power. should the link need the 60mhz clock to continue during the serial mode of operation, the clocksuspendm bit[3] of the interface control register should be set before entering a serial mode. if set, the 60 mhz clock will be present during serial modes. in serial mode, interrupts are possible from unmasked source s. the state of each interrupt source is sampled prior to the assertion of dir and this is compared against the asynchronous level from interrupt source. exiting the serial modes is the same as exiting low power mode. the link must assert stp to signal the phy to exit serial mode. then the phy can accept a command, dir is de-asserted and the phy will wait until the link de-asserts stp to resume synchronous ulpi operation. 6.1.10.1 3pin fs/ls serial mode three pin serial mode utilizes the data bu s pins for the serial functions shown in table 6-7, "pin definitions in 3-pin serial mode" . table 6-7: pin definition s in 3-pin serial mode signal connected to direction description tx_enable data[0] in active high transmit enable data data[1] i/o tx differential data on dp/dm when tx_enable is high rx differential data from dp/dm when tx_enable is low se0 data[2] i/o tx se0 on dp/dm when tx_enable is high rx se0 from dp/dm when tx_enable is low interrupt data[3] out asserted when any unmasked interrupt occurs. active high
? 2014-2015 microchip technology inc. ds00001783b-page 33 USB3300 6.1.11 reset pin the reset input of the USB3300 may be asynchronously assert ed and de-asserted so long as it is held in the asserted state continuously for a duration grea ter than one clko ut clock cycle. the reset inpu t may be asserted when the USB3300 clkout signal is not active (i.e. in the suspend stat e caused by asserting the sus pendm bit) but reset must only be de-asserted when the USB3300 clkout signal is active a nd the reset has been held asserted for a duration greater than one clkout clock cycle. no other phy digital input signals may change state for two clkout clock cycles after the de- assertion of the reset signal. 6.2 hi-speed usb transceiver the microchip hi-speed usb 2.0 tr ansceiver consists of four blo cks in the lower right corner of figure 6-1, "simplified USB3300 architecture" . these four blocks are labeled hs xcvr, fs/ls xcvr, resistors, and bias gen. 6.2.1 high speed and fu ll speed transceivers the USB3300 transceiver meets all requi rements in the usb 2.0 specification. the receivers connect directly to the usb cable. this bloc k contains a separate differential receiver for hs and fs mode. depending on the mode, the selected receiver provides the serial data st ream through the multiplexer to the rx logic block. the fs mode section of the fs/hs rx block al so consists of a single-ended receiver on each of the data lines to determine the correct fs linestate. for hs mode support, the fs/hs rx block contains a squelch circuit to insure that noise is ne ver interpreted as data. the transmitters connect directly to the usb cable. the bl ock contains a separate differential fs and hs transmitter which receive encoded, bit stuffed, se rialized data from the tx logic block and transmit it onto the usb cable. 6.2.2 terminati on resistors the USB3300 transceiver fully integr ates all of the usb te rmination resistors. the USB3300 includes 1.5k ? pull-up resistors on both dp and dm and a 15k ? pull-down resistor on both dp and dm. the 45 ? high speed termination resis- tors are also integrated. these resistors require no tuning or trimming by the link. the stat e of the resistors is deter- mined by the operating mode of the phy. the possi ble valid resistor combinations are shown in table 6-8, "dp/dm termination vs. signaling mode" . operation is guaranteed in the confi gurations given in the table below. ? rpu_dp_en activates the 1.5k ? dp pull-up resistor ? rpu_dm_en activates the 1.5k ? dm pull-up resistor ? rpd_dp_en activates the 15k ? dp pull-down resistor ? rpd_dm_en activates the 15k ? dm pull-down resistor ? hsterm_en activates the 45 ? dp and dm high speed termination resistors table 6-8: dp/dm termination vs. signaling mode signaling mode register settings r esistor settings xcvrselect[1:0] termselect opmode[1:0] dppulldown dmpulldown rpu_dp_en rpu_dm_en rpd_dp_en rpd_dm_en hsterm_en general settings tri-state drivers xxbxb01bxbxb0b0b0b0b0b power-up or vbus < v sessend 01b0b00b1b1b0b0b1b1b0b host settings host chirp 00b0b10b1b1b0b0b1b1b1b host hi-speed 00b0b00b1b1b0b0b1b1b1b host full speed x1b1b00b1b1b0b0b1b1b0b host hs/fs suspend 01b1b00b1b1b0b0b1b1b0b host hs/fs resume 01b1b10b1b1b0b0b1b1b0b
USB3300 ds00001783b-page 34 ? 2014-2015 microchip technology inc. 6.2.3 bias generator this block consists of an internal bandgap reference circuit used for generating the driver cu rrent and the biasing of the analog circuits. this block requires an external 12k , 1% tolerance, external referenc e resistor connected from rbias to ground. 6.3 crystal oscillator and pll the USB3300 uses an internal crystal driver and pll sub- system to provide a clean 480mhz reference clock that is used by the phy during both transmit and receive. the usb330 0 requires a clean 24mhz crystal or clock as a frequency reference. if the 24mhz reference is noisy or off frequency the phy may not operate correctly. the USB3300 can use either a crystal or an external clock oscillator for the 24mhz reference. the crystal is connected to the xi and xo pins as shown in the application diagram, figure 7-1 . if a clock oscillator is used the clock should be connected to the xi input and the xo pin left floating. when a external clock is used the xi pin is designed to be driven with a 0 to 3.3 volt signal. when using an external clock the us er needs to take care to ensure the external clock source is clean enough to not corrupt the high speed eye performance. once the 480mhz pll has locked to the correct frequency it will drive the clkout pi n with a 60mhz clock. the USB3300 is guaranteed to start the clock within the time specified in table 5-2, "electrical ch aracteristics: clkout start-up" . the USB3300 does not support using an external 60mhz clock input. host low speed 10b1b00b1b1b0b0b1b1b0b host ls suspend 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b host ls resume 10b1b10b1b1b0b0b1b1b0b host test j/test_k 00b0b10b1b1b0b0b1b1b1b peripheral settings peripheral chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b 0b peripheral hs 00b 0b 00b 0b 0b 0b 0b 0b 0b 1b peripheral fs 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b peripheral hs/fs suspend 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b peripheral hs/fs resume 01b 1b 10b 0b 0b 1b 0b 0b 0b 0b peripheral ls 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b peripheral ls suspend 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b peripheral ls resume 10b 1b 10b 0b 0b 0b 1b 0b 0b 0b peripheral test j/test k 00b 0b 10b 0b 0b 0b 0b 0b 0b 1b otg device, peripheral chirp 00b 1b 10b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral hs 00b 0b 00b 0b 1b 0b 0b 0b 1b 1b otg device, peripheral fs 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral hs/fs suspend 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral hs/fs resume 01b 1b 10b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral test j/test k 00b 0b 10b 0b 1b 0b 0b 0b 1b 1b note: this is the same as table 40, sectio n 4.4 of the ulpi 1.1 specification. table 6-8: dp/dm termination vs. signaling mode (continued) signaling mode register settings r esistor settings xcvrselect[1:0] termselect opmode[1:0] dppulldown dmpulldown rpu_dp_en rpu_dm_en rpd_dp_en rpd_dm_en hsterm_en
? 2014-2015 microchip technology inc. ds00001783b-page 35 USB3300 for host applications the u sb3300 implements the ulpi autoresume bit in the interface control register. the default autoresume state is 0 and this bit should be enabled for host a pplications. for more details please see sections 7.1.77 and 7.9 of the usb specification. 6.4 internal regulators and por the USB3300 includes an integrated set of built in power management functions, includ ing a por generator. internal regulators enable the USB3300 to be powered from a single 3. 3 volt power supply, thereby r educing the bill of materials and simplifying product design. 6.4.1 internal regulators the USB3300 has two internal regulators that create two 1.8v outputs (labeled vdd1.8 and vdda1.8) from the 3.3volt power supply input (vdd3.3). each regulator requires an ex ternal 4.7uf +/-20% low esr bypass capacitor to ensure stability. x5r or x7r ceramic capacitors are recommended sinc e they exhibit an esr lower that 0.1ohm at frequencies greater than 10khz. 6.4.2 power on reset (por) the USB3300 provides an internal por ci rcuit that generates a reset pulse once the phy supplies are stable. this reset will set all of the ulpi registers to thei r default values and start the phy in normal operation. cycling the 3.3 volt power supply is the only method for the phy to reset the ulpi regist ers to their default states. th e link can write the registers to their default states at any time in normal operation. the reset pin has the same functi onality as the reset register in the function control register. 6.5 usb on-the-go (otg) module the USB3300 provides support for usb otg. otg allows th e USB3300 to be dynamically configured as a host or a device depending on the type of cable inse rted into the mini-ab connector. when t he mini-a plug of a cable is inserted into the mini-ab connector, the usb device becomes the a-devic e. when a mini-b plug is inserted, the device becomes the b-device. the otg a-device behaves simi lar to a host while the b-device behaves similar to a peripheral. the dif- ferences are covered in the otg supplement. the otg module meets all the requirements in the ?on-the- go supplement to the usb 2. 0 specification?. in applica- tions where only host or device is required, the otg module is unused. note: the specific capacitor recommendations for each pin are detailed in table 3-1, "USB3300 pin definitions 32-pin qfn package" , and shown in figure 7-1: USB3300 application diagram (peripheral) on page 40 . the USB3300 regulators are designed to generate a 1.8 volt supply for the USB3300 only. using the reg- ulators to provide current for other circuits is not recommended and microchip does not guarantee usb performance or regulator stability.
USB3300 ds00001783b-page 36 ? 2014-2015 microchip technology inc. the otg module can be br oken into 4 main blocks; id de tection, vbus contro l, driving external vbus, and external vbus detection. each of these blo cks is covered in the sections below. 6.5.1 id detection the USB3300 provides an id pin to determine the type of us b cable connected. when the mini-a plug of a usb cable is inserted into the mini-ab connector, the id pin is shorted to ground. when the mini-b plug is inserted into the mini- ab connector, the id pin is allowed to float. . the USB3300 provides an integrated pull-up resistor and a comp arator to detect if the id pin is floating or grounded. an integrated pull-up resistor is provided to pull the id pin high to vdd3.3 when a mini-b plug is inserted and the cable is floating. when a mini-a plug is connected, the pull-up re sistor will be overpowered and the id pin will be brought to ground. to save current when a mini-a plug is inserted, the id pull-up resistor can be disabled by clearing the idpullup figure 6-10: USB3300 on-the-go module table 6-9: idgnd vs. usb cable type usb plug otg role id voltage idgnd ahost0 0 b peripheral 3.3 1 extvbus cpen r=75k r>=656 r>=281 otg module vbus id vdd33 rxcmd vbusvalid indicatorcomplement [useexternalvbusindicato r, indicatorpassthru] [0, x] vbusvalid sessvalid sessend idpullup dischrgvbus drvvbus drvvbusexternal idgnd chrgvbus 0.5v 1.4v 4.575v 0.6v r=100k [1, 0] [1, 1] r>1m
? 2014-2015 microchip technology inc. ds00001783b-page 37 USB3300 bit in the otg control register. to preven t the id pin from floating to a random va lue, a weak pull-up resistor is provided at all times. the circuits related to the id comparator are shown in figure 6-10, "USB3300 on-the-go module" and their related parameters are shown in table 5-6, "otg electrical characteristics" . the status of idgnd can be read by reading the ulpi usb interrupt stat us register, bit 4. it can also be set to generate an interrupt, in host mode, when idgnd changes with the ulpi interrupt enable registers. 6.5.2 vbus control the USB3300 includes all of the vbus comparators require d for otg. the vbusvld, sessvld, and sessend compara- tors are fully integrated into the USB3300. these comparators are used to ensure the vbus voltage is the correct value for proper usb operation. the vbusvld comparator is used by the link, when configur ed as an a device, to ensure that the vbus voltage on the cable is valid. the sessvld comparator is used by the link when configured as both an a or b device to indicate a ses- sion is requested or valid. finally th e sessend comparator is used by the b- device to indicate a usb session has ended. also included in the vbus control block are the resistors used for vbus pulsing in srp. the resistors used for vbus pulsing include a pull-down to ground and a pull-up to vdd3.3. 6.5.2.1 sessend comparator the sessend comparator is designed to trip when vbus is less than 0.5 volts. when vbus goes below 0.5 volts the ses- sion is considered to be ended and sessend will transition fr om 0 to 1. the sessend compatator can be disabled by clearing this bit in both the rising and falling interrupt enab le registers. when disabled th e sessend bit in the interrupt status register will read 0. the sessend comparator trip points are detailed in table 5-6 . 6.5.2.2 sessvld comparator the sessvld comparator is used when the phy is configured as both an a and b device. when configured as an a device, the sessvld is used to detect session request protocol (srp). when co nfigured as a b device, sessvld is used to detect the presence of vbus. the sessvld interrupts can be disabled by clearing this bit in both the rising and falling interrupt enable registers. when the interrupts are disabled, the sessvld comparator is not disabled and its state can be read in the interrupt status register. the se ssvld comparator trip point is detailed in ta b l e 5 - 6 . 6.5.2.3 vbusvld comparator the final vbus comparator is the vbusvld comparator. this comparator is only used when configured as an a-device. in the otg protocol the a-device is resp onsible to ensure that the vbus voltage is within a certain range. the vbusvld comparator can be disabled by clearing both the rising and fa lling edge interrupts. when disabled a read of bit 1, in the interrupt status register will return a 0. the vbusvld comparator trip points are detailed in ta b l e 5 - 6 . when the a-device is able to provide 8-100ma it must ensur e vbus doesn?t go below 4.4 vo lts. if the a-device can pro- vide 100-500ma on vbus it must ensure that vbus does not go below 4.75 volts. the internal vbus comparator is designed to ensure that vbus remains above 4.4 volts. if the design is required to sup- ply over 100ma the USB3300 provides an input for a more a ccurate vbus comparator or fault (over current) detection described in section 6.5.4, "external vbus indicator" . 6.5.2.4 vbus pull-up and pull-down resistors in addition to the internal vbus comparators the USB3300 also includes the integrated vbus pull-up and pull-down resis- tors used for vbus pulsing. to discharge the vbus voltage, so that a session request can begin, the USB3300 provides a pull-down resistor from vbus to ground. this resistor is controlled by the dischargevbus bit 3 of the otg control register, defined in the ulpi specifications. the pull-up re sistor is connected between vbus and vdd3.3. this resistor is used to pull vbus above 2.1 volts so that the a-devi ce knows that a usb session has been requested. the state of the pull-up resistor is controlled by the bit 4 chargevbus of the otg control register, defi ned in the ulpi specifications. the pull-up and pull-down resistor values are detailed in ta b l e 5 - 6 . note: the otg supplement specifies a voltage range for a-device session valid and b-device session valid comparator. the USB3300 phy combines the two comparators into one and uses the narrower threshold range.
USB3300 ds00001783b-page 38 ? 2014-2015 microchip technology inc. 6.5.2.5 vbus input impedance the otg supplement requires an a-device that supports session request protocol to have an input impedance less than 100kohm and greater the 40kohm to ground. in addition, if configured as a b-device, the phy cannot draw more then 150ua from vbus. the USB3300 provides a 75k ? nominal resistance to ground which meets the above require- ments, see ta b l e 5 - 6 . 6.5.3 driving external vbus when a system is operating as a host, it is required to source 5 volts on vbus. the USB3300 fully supports vbus power control using external devices. the USB3300 provides an active high control signal, cpen, which is dedicated to controlling the vbus supply when conf igured as an a-device. the USB3300 also supports external vbus fault detec- tion detailed in section 6.5.4 . cpen is asserted when the ulpi otg control register bit 5 drvvbus or bit 6, drvvbusexternal is set high. to be com- patible with link designs that support both internal and external vbus supplies the drvvbus and drvvbusexternal bits in the otg control register are or?d together. this enables th e link to set either bit to access the external vbus enable (cpen.) this logic is shown in figure 6-10, "USB3300 on-the-go module" . drvvbus and drvvbusexternal are set to 0 on por. 6.5.4 external vbus indicator the USB3300 has fully implemented the ex ternal vbus detection described in the ulpi 1.1 specification. the block dia- gram of the external vbus detection is shown in figure 6-10 and in ta b l e 6 - 1 0 . note 6-1 microchip does not recommend using the externalvbus signal qualified with the internal vbusvld comparator. note 6-2 a peripheral should not use vbusvld to begin op eration. the peripheral should use sessvld because the internal vbusvld threshold can be above the v bus voltage required for usb peripheral operation. a host phy may use an active high or low fault by setting the indicatorcomplement bit [5] in the interface control reg- ister. also this implementation supports the indicatorpassthru bit [6] in the interface control register, which allows a choice of having the external vbus input qualified (and?ed) wit h the external vbus comparator output. to use the external vbus input the useexternalvbusindicator bit [7] must be set in the otg control register. the default is not to use this input. the extvbus pin has a built in pull down resistor that is controlled by the useexternalvbusindicator bit [7] of the otg control register. when useexternalvbusindicator is set to 0 (default) the pull down resistor is activated to prevent the pin from floating when it is unused. when useexternalvbusindicator is set to 1 the pull down resistor is disconnected. table 6-10: external vbus indicator logic typical application use external vbus indicator indicator pass thru indicator complement rxcmd vbus valid encoding source otg device 0 x x internal vbusvld comparator (default) 1 1 0 external active high vbusvld signal 1 1 1 external active low vbusvld signal 1 0 0 external active high power fault signal qualified with internal vbusvld comparator. ( note 6-1 ) 1 0 1 external active low power fault signal qualified with internal vbusvld comparator. ( note 6-1 ) standard host 1 1 0 external active high power fault signal 1 1 1 external active low power fault signal standard peripheral 0 x x internal vbusvld comparator. this should not be used by the link. ( note 6-2 )
? 2014-2015 microchip technology inc. ds00001783b-page 39 USB3300 7.0 application notes the USB3300 requires few external components as shown in the application diagrams. in some applications, the power supplied on the vbus and gnd pins of the usb connector is used as the source of system power. the usb2.0 standard restricts the voltage at the vbus pin to a maximum value of 5. 25v. in some applications, it may be required to provide protection to the USB3300 vbus pin if the vbus voltage exceeds the usb2.0 specifications. one method of protecting the vbus pin from excessive voltage (transients) is to place a resistor (r vbus ) in series as shown in figure 7-1, "USB3300 application diagram (per ipheral)" and figure 7-2, "USB3300 application diagram (host or otg)". the resistor provides protecti on against transients that exceed the value of v vbus provided in ta b l e 4 - 2, "recommended operating conditions" . when r vbus is installed, the transient mu st not be allowed to exceed the value of v vbus for longer than 500 s. to protect the vbus pin against a steady state voltage on the usb connector that exceeds the value of v vbus provided in table 4-2 , an over voltage protection (ovp) co mponent can be used as shown in figure 7-3, "USB3300 application diagram (peripheral with over voltage protection)". in addition to the capacitors shown in the application di agrams, each vdd pin should have an additional capacitor to ground, of value 0.01 or 0.1 f (not shown for clarity). approximately equal numbers of each value should be used. table 7-1: component values in application diagrams reference designator value description notes c out 4.7 f bypass capacitors to ground (<1 esr) for regulator stability. place as close as possible to the phy. c vbus see table 7-2, "capacitance values at vbus of usb connector" capacitor to ground required by the usb specification. microchip recommends <1 esr. place near the usb connector. c byp system dependent. bypass capacitor to grou nd. place as close as possible to the phy. c dc_block system dependent. the usb connector housing may be ac-coupled to the device ground. industry convention is to ground only the host side of the cable shield. r vbus max of 820 in host or otg applications. series resistor to reduce any transient voltage on the vbus pin of the USB3300. the transient must not be allowed to exceed the value of v vbus for longer than 500 s id pin okay to leave no connection (nc) in device mode. table 7-2: capacitance values at vbus of usb connector mode min value max value host 120 f device 1 f10 f otg 1 f6.5 f
USB3300 ds00001783b-page 40 ? 2014-2015 microchip technology inc. 7.1 application diagrams figure 7-1: USB3300 application diagram (peripheral) link controller USB3300 rbias dir nxt stp clkout data7 data6 data5 data4 data3 data2 data0 data1 vdd3.3 vdd3.3 vbus dm dp id reset usb receptacle dm dp dir nxt stp clkout data7 data6 data5 data4 data3 data2 data0 data1 7 8 32 gnd flag 2 3 vbus 1 shield gnd 16 6 4 5 c byp c vbus 3.3v supply r vbus may be installed in this configuration to assist in protecting the vbus pin. 820 ohms will protect against vbus transients up to 8.5v. 10k ohms will protect against transients up to 10v. vdda1.8 29 c dc_block 12.0k 1% steady state voltage at the vbus pin must not be allowed to exceed v vbus . r vbus nc 17 18 19 20 21 22 23 24 13 11 12 14 9 c out xi 28 cpen 3 nc xo 27 1m c load c load reg_en vdd3.3 30 31 vdd1.8 26 12 vdd1.8 15 c out vdd3.3 25 extvbus 10 nc the capacitor c vbus must be installed on this side of r vbus .
? 2014-2015 microchip technology inc. ds00001783b-page 41 USB3300 figure 7-2: USB3300 application diagram (host or otg) link controller USB3300 rbias dir nxt stp clkout data7 data6 data5 data4 data3 data2 data0 data1 vdd3.3 vdd3.3 vbus dm dp id reset usb receptacle dm dp dir nxt stp clkout data7 data6 data5 data4 data3 data2 data0 data1 7 8 32 gnd flag 2 3 vbus 1 id 16 6 4 5 c byp c vbus 3.3v r vbus may be installed to assist in protecting the vbus pin. 820 ohms will protect against vbus transients up to 8.5v. vdda1.8 29 12.0k 1% steady state voltage at the vbus pin must not be allowed to exceed v vbus . r vbus 17 18 19 20 21 22 23 24 13 11 12 14 9 c out xi 28 xo 27 1m c load c load reg_en vdd3.3 30 31 vdd1.8 26 12 vdd1.8 15 c out vdd3.3 25 the capacitor c vbus must be installed on this side of r vbus . cpen 3 vbus switch out en in extvbus 10 flg gnd shield 4 5v
USB3300 ds00001783b-page 42 ? 2014-2015 microchip technology inc. figure 7-3: USB3300 application diag ram (peripheral with over voltage protection) link controller USB3300 rbias dir nxt stp clkout data7 data6 data5 data4 data3 data2 data0 data1 vdd3.3 vdd3.3 vbus dm dp id reset usb receptacle dm dp dir nxt stp clkout data7 data6 data5 data4 data3 data2 data0 data1 7 8 32 gnd flag 2 3 vbus 1 shield gnd 16 6 4 5 c byp c vbus 3.3v supply vdda1.8 29 c dc_block 12.0k 1% steady state voltage at the vbus pin must not be allowed to exceed v vbus . nc 17 18 19 20 21 22 23 24 13 11 12 14 9 c out xi 28 cpen 3 nc xo 27 1m c load c load reg_en vdd3.3 30 31 vdd1.8 26 12 vdd1.8 15 c out vdd3.3 25 extvbus 10 nc the capacitor c vbus must be installed on this side of r vbus . over-voltage device may be desired to protect against out-of-spec chargers. optional over-voltage protection
? 2014-2015 microchip technology inc. ds00001783b-page 43 USB3300 7.2 multi-port applications to support multiple ports a single USB3300 host can be co mbined with one of microchip?s many hub products to expand the number of ports. microchip has 2-port, 3-port, 4-port, and 7-port hub designs which can be used to expand the num- ber of ports in a design. using a microchip hub to expand the number of ports allows a single link to run several usb devices without a separate link to support each usb port. another advantage of using a microchip hub is on products where the main board is not located near the usb ports. the USB3300 can be placed on the main board with the link asic and the hub can be placed on a separate board next to the usb ports. the only data connection required between the boards is dp and dm. the cpen output of the USB3300 is optional and can be used to turn the hub on or off to lower current when the usb connection isn?t needed. 7.3 evaluation board an evaluation board, evb-usb3 300, is available for building a prototype system with the USB3300. the evaluation board provides an industry standard t&mt connector to in terface a ulpi link controller and a mini-ab connector for the usb cable. a 500ma fault protected 5v vbus switch that is controlled by the USB3300 is also included. 7.4 esd performance the USB3300 is protected from esd strikes. by eliminating the requirement for ex ternal esd protection devices, board space is conserved, and the board m anufacturer is enabled to reduce cost. the advanced esd structures integrated into the USB3300 protect the device whet her or not it is powered up. when the USB3300 is not powered, the digital i/o pins are loaded by the esd structures, and must not be driven by external signals. 7.4.1 human body model (hbm) performance hbm testing verifies the ability to withs tand the esd strikes like t hose that occur during handling and manufacturing, and is done without power applied to the ic. to pass the tes t, the device must have no ch ange in operation or perfor- mance due to the event. all pins on the USB3300 provide 8kv hbm protection. figure 7-4: expanding down stream ports for usb3 300 host applications USB3300 dp dm cpen usbdp0 usbdm0 vbus_det soc w/ ulpi link dp dm usb port 1 usbdp1 usbdn1 dir nxt stp data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] clock dir nxt stp data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] clock usb2502 dp dm usb port 2 usbdp2 usbdn2 dp dm usb port 3 usbdp3 usbdn3 dp dm usb port 4 usbdp4 usbdn4 dp dm usb ports 5-7 usbdp5-7 usbdn5-7 usb2507 usb2503 usb2504
USB3300 ds00001783b-page 44 ? 2014-2015 microchip technology inc. 7.4.2 iec61000-4-2 performance the iec61000-4-2 esd specification is an international stand ard that addresses system-level immunity to esd strikes while the end equipment is operational. in contrast, the hbm esd tests are performed at the device level with the device powered down. microchip contracts with independent laboratories to test the USB3300 to iec61000-4-2 in a working system. reports are available upon request. please contact your microchi p representative, and request information on 3rd party esd test results. the reports sh ow that systems design ed with the USB3300 c an safely dissipate 1 5kv air discharges and 8kv contact discharges per the iec61000-4-2 specific ation without additional board level protection. both air discharge and contact discharge test techniques for applying stress conditions are defined by the iec61000-4- 2 esd document. 7.4.2.1 air discharge to perform this test, a charged electrode is moved close to th e system being tested until a sp ark is generated. this test is difficult to reproduce because the discharge is influenced by such factors as humidity, the speed of approach of the electrode, and constructi on of the test equipment. 7.4.2.2 contact discharge the uncharged electrode first contacts the pin to prepare this test, and then the probe tip is energized. this yields more repeatable results, and is the preferred test method. the independent test laboratories cont racted by microchip provide test results for both types of discharge methods.
? 2014-2015 microchip technology inc. ds00001783b-page 45 USB3300 8.0 package outline the USB3300 is offered in a compact 32 pin qfn package. figure 8-1: USB3300-ezk 32-pin qfn packag e outline, 5 x 5 x 0.9mm body (1 of 2) note: for the most current package drawings, see the microchip packaging specification at http://www.microchip.com/packaging
USB3300 ds00001783b-page 46 ? 2014-2015 microchip technology inc. figure 8-2: USB3300-ezk 32-pin qfn packag e outline, 5 x 5 x 0.9mm body (2 of 2) note: for the most current package drawings, see the microchip packaging specification at http://www.microchip.com/packaging
? 2014-2015 microchip technology inc. ds00001783b-page 47 USB3300 figure 8-3: qfn, 5x5 taping di mensions and part orientation
USB3300 ds00001783b-page 48 ? 2014-2015 microchip technology inc. appendix a: data sheet revision history table a-1: revision history revision section/figure/entry correction ds00001783b (06-03-15) section , "product identifica- tion system," on page 51 updated ordering code temperature information. ds00001783a (07-08-14) replaces previous smsc version rev. 1.1 (01-24-13) document converted to microchip template reel drawings and mention of reel quantity removed from package outline chapter. rev. 1.1 (01-24-13) section 5.1, "piezoelectric resonator for internal oscillator," on page 15 added section. rev. 1.08 (11-07-07) table 3-1, "USB3300 pin definitions 32-pin qfn package" description for pins 15, 26, 29 and 31 modified. rev. 1.08 (10-25-07) table 3-1, "USB3300 pin definitions 32-pin qfn package" description for ?reg_en? (pin 31) modified. rev. 1.07 (09-26-07) section 7.4, "esd performance" added last sentence warning against multiplexing digital i/o signals. rev. 1.07 (09-26-07) figure 7-2, "USB3300 application diagram (host or otg)" and figure 7-3, "USB3300 application diagram (peripheral with over voltage protection)" added information on r vbus. rev. 1.07 (09-25-07) application notes on page 39 and figure 7-1, "USB3300 application diagram (peripheral)" changed to include information on r vbus . rev. 1.07 (09-20-07) table 3-1, "USB3300 pin definitions 32-pin qfn package" changed description of reset. rev. 1.07 (09-20-07) added tape & reel pn and drawings. rev. 1.06 (05-07-07) ?usb2.0? changed to ?usb 2.0? rev. 1.06 (07-19-06) applications first sentence modified from: ?the USB3300 is targeted for any application where a hi-speed usb connection is desired and when board space and interface pins must be minimized.? to: ?the USB3300 is the ideal companion to any asic, soc or fpga solution designed with a ulpi hi-speed usb host, peripheral or otg core.? rev. 1.06 (07-18-06) applications added ?pdas?, removed ?e ntertainment devices?, added ?digital? to ?still and video games?. rev. 1.06 (07-18-06) features moved ?applications? to cover; re-ordered several features. rev. 1.06 (07-17-06) features and general description on page 4 referenced industrial operating temperature. table 4-1, "maximum guaranteed ratings" changed operating temperature from ?0 to 70? to ?- 40 to 85? table 4-2, "recommended operating conditions" changed operating temperature from ?0 to 70? to ?- 40 to 85?
? 2014-2015 microchip technology inc. ds00001783b-page 49 USB3300 rev. 1.05 (05-26-06) table 4-1 added esd and latch-up entries section 7.4, "esd performance" added section 7.4 cover - features: esd protection levels of 8kv hbm without external protection devices removed mention of wrapper available. (also removed from section 1 and 6.1.1) added bullets on esd and latch-up. usb interrupt status register: address = 13h (read only with auto clear) on page 23 corrected title of section rev 1.04 (02-28-06) table 6-5, "ulpi rx cmd encoding" corrected cmd encoding for data[5:4] usb interrupt status register: address = 13h (read only with auto clear) corrected to read ?status re gister? instead of ?latch register? USB3300 pin definitions 32- pin qfn package changed pin 31 from vcca1.8 to reg_en. changed pin description to describe reg_en operation table 8.1, "32 terminal qfn package parameters" updated package dimensions per package data sheet located in specifications database figure 3.1, "USB3300 pin diagram" changed pin 31 in figure 3.1 to be named ?reg_en?. table 5-1, "electrical characteristics: supply pins" added max current information rev. 1.03 (05-11-05) table 3-1, "USB3300 pin definitions 32-pin qfn package" modified description for pin 29 (wording changed from ?digital? to ?analog?) table 6-2, "ulpi interface timing" add min value to output delay cover - title added otg to title changed to otg version of usb logo. table a-1: revision history (continued) revision section/figure/entry correction
USB3300 ds00001783b-page 50 ? 2014-2015 microchip technology inc. the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep custom ers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notifi- cation? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://www.microchip.com/support
? 2014-2015 microchip technology inc. ds00001783b-page 51 USB3300 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: USB3300 temperature range: blank = -40 c to +85 c (industrial) package: ezk = 32-pin qfn tape and reel option: blank = standard packaging (tray) tr = tape and reel (1) examples: a) USB3300-ezk 32-pin qfn rohs compliant package b) USB3300-ezk-tr 32-pin qfn (tape & reel) rohs compliant package note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the dev ice package. check with your microchip sa les office for package availability with the tape and reel option. part no. [x] xxx package temperature range device [x] (1) tape and reel option - -
ds00001783b-page 52 ? 2014-2015 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip make s no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising from this information and its use. use of micro- chip devices in life support and/or safety applications is entirely at the buyer?s ri sk, and the buyer agrees to defend, indemn ify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, impl icitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashf lex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technolog y incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered tr ademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code gener ation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, view span, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a regi stered trademark of microchip tech nology inc. in other countries. gestic is a registered trademarks of microc hip technology germany ii gmbh & co. kg, a s ubsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2014-2015, microchip technology incorporated, pr inted in the u.s.a., all rights reserved. isbn: 9781632774491 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature ma y be a violation of the digita l millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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